Clockless VLSI Design
نویسندگان
چکیده
26 0740-7475/03/$17.00 © 2003 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers FOR THE PAST TWO DECADES, digital design has focused primarily on synchronous, clocked architectures. However, because clock rates have significantly increased while feature size has decreased, clock skew has become a major problem. To achieve acceptable skew, high-performance chips must dedicate increasingly larger portions of their area to clock drivers, thus dissipating increasingly higher power, especially at the clock edge, when switching is most prevalent. As this trend continues, the clock is becoming more difficult to manage, causing renewed interest in asynchronous digital design. Researchers have demonstrated that correct-by-construction asynchronous paradigms, particularly null convention logic (NCL), require less power, generate less noise, produce less electromagnetic interference, and allow easier reuse of components than their synchronous counterparts, without compromising performance.1 Furthermore, we expect these paradigms to allow much greater flexibility in the design of complex circuits such as SoCs. Because these circuits are delay insensitive, they should drastically reduce the effort required to ensure correct operation under all timing scenarios, compared to equivalent synchronous designs. Also, the self-timed nature of correctby-construction SoCs should allow designers to reuse previously designed and verified functional blocks in subsequent designs, without significant modifications or retiming effort within a reused functional block. Such SoCs might also provide simpler interfacing between the digital core and nontraditional functional blocks. One of the first tasks necessary to help integrate NCL into the semiconductor design industry is to develop and characterize the key components of a reusable-design library. Of fundamental importance are arithmetic circuits, including the multipliers we describe in this article and the ALUs we described elsewhere.2 Here, we present 4-bit × 4-bit unsigned multipliers that we designed using the delayinsensitive NCL paradigm. They represent bit-serial, iterative, and fully parallel multiplication architectures. The figures depicting each multiplier component are available at http://www.ece.umr.edu/~smithsco.
منابع مشابه
A High-Speed Clockless Serial Link Transceiver
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed, serial off-chip buses. While synchronous transceivers commonly use multi-phase clocks to control ...
متن کاملPower-Efficient Design of a Clockless NoC Router with a New Integrated Flow
The downscaling of silicon technology and the capacity to build entire systems on a chip have made intrachip communication a relevant research topic. Besides, technology challenges point to the fast adoption of non-synchronous networks on chip (NoCs), using either globally asynchronous, locally synchronous (GALS) or even clockless approaches. However, clockless circuit design with current autom...
متن کامل25 Years Ago: the First Asynchronous Microprocessor
Twenty-five years ago, in December 1988, my research group at Caltech submitted the world’s first asynchronous (“clockless”) microprocessor design for fabrication to MOSIS. We received the chips in early 1989; testing started in February 1989. The chips were found fully functional on first silicon. The results were presented at the Decennial Caltech VLSI Conference in March of the same year. Th...
متن کاملThe MANGO ClocklessNetwork-on-Chip:*0.5exConcepts and Implementation
Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting IP cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. In...
متن کاملYield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly desirable to have an adequate and specific pulse fault rate model for establishing a sound theoretical foundation for clockless wave pipeline design for reliability. The pulse fault model is thoroughly identified as the ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2001